This invention relates generally to computer memory, and more specifically, to write pausing and pre-empting techniques to improve read latency of memory systems.
Limited lifetime computer storage devices include, but are not limited to, flash memory (e.g., not-and or “NAND” flash memory, and not-or or “NOR” flash memory) and phase change memory (PCM). Limited lifetime memory technologies may benefit from iterative write techniques (commonly referred to as “write-and-verify”) that are comprised of a sequence of write and read operations. Iterative write techniques may allow a controller for the memory to store a desired value with an increased accuracy, since the read operations offer a feedback mechanism that can be used to reduce errors in the writing process.
Many of the emerging non-volatile memory technologies (e.g., flash and PCM) have asymmetric latency for read and write requests. Servicing a write request typically takes four to sixteen times the amount of time that it takes to service a read request. When a write request is scheduled to a bank of such slow-to-write memory, the bank is busy until the write request is completed. If another read or write request arrives at the same bank after the write is scheduled, that request has to wait until the current request is serviced. Thus, the slow writes can increase contention and increase the effective latency for subsequent read and write requests. While increased latency due to contention can generally be tolerated for write requests by using buffers, the increased latency for a read request may have bigger impact on overall system performance because reads are often in a critical path of a program being executed.